Nintendo DS FPGA Core

Rober Peip AKA FPGAzumSpass is coding an open-source FPGA implementation of the Nintendo DS, as a follow-up to his FPGA GBA core. Although the DS core is young and progress will be slow considering the complexity of the hardware, he does now have it booting games, and he posted a video of it running Ace Attorney Edgeworth.

It is being built on the Nexys Video Develpment Board, with an Artix7-200 FPGA and dedicated DDR3 RAM. When complete he plans to bring it to MiSTer, with some limitations. It will run on MiSTer, but the powerful 3D games may run at a reduced framerate due to RAM limitations, as explained below.

Platform is currently the Nexys Video with an Artix7-200 FPGA and dedicated DDR3.

FPGA Usage:
LUTs: 52000/134000 (should be comparable to ~80k LEs in Cyclone 5)
FF: 40000/267000
BRAM: 322/365
DDR3 holds: Gamerom, 4Mbyte external Ram, Savememory, Firmware, Savestate

Sourcecode will be uploaded soon.

I’m still not sure if I start porting to Mister before or after I implement 3D. However, as the Mister FPGA has not enough internal Ram to fit the 9(!) Videorams, expect lower framerates, depending on how frequent the game accesses videorams for drawing.

…I started by building my own emulator(C++) that is “compatible” to an existing emulator. Also there is a great documentation from Martin Korth. So i could find out how everything works. In the process of creating this emulator, i noted everything that is wrong/questionable, so i can correct it later on when the games are running. Then i did the same with the FPGA core: make it compatible to my emulator and note everything that must be changed for accuracy when the games are running.

So my main goal is always game compatibility. Not just because it’s more fun, but also because when most games are running, the functionality is there. Altering timing isn’t difficult when it’s known what the correct timing is and if not, try-and-error works better with a stable base.

On the challenge of porting it to MiSTer, he writes:

The DS has a hardware to display 3D (textured polygons). Currently i have only implemented the 2D drawing parts. The workaround for Mister is to use one or two sdram modules. But as there are 9 VRams running at 33Mhz with 1 clock cycle latency, even 2 Sdrams cannot handle them all at the correct speed. The workaround is to make the drawing “best effort”. Don’t expect 100% accuracy with it, but games that don’t use ALL graphical capabilities at the same time, should be playable. Also some games are probably also playable with lower FPS, like strategic games or turnbased RPGs…because the FPGA cannot handle all 9 [VRAMs] internally. I will probably still try to fit the smaller 5 into the FPGA, so hopefully only the 4 large have to be put in SDRams.

Source: SmokeMonster Discord, Reddit, YouTube